? at a glance ? product brief S19235 oc-192 sonet/sdh/fec/gbe 16-bit transceiver empowering intelligen t optical networks 1 pb1204_v2.01_10/03/03 description the S19235 sonet/sdh/fec and 10 gigabit ethernet (gbe) transceiver is one of the latest additions to amcc?s superphy tm product family. the S19235 device provides fully integrated serialization/de-serialization capabilities for low power intermediate and long reach oc-192 applications. the device performs all necessary parallel-to-serial and serial-to-parallel functions in conformance with sonet/sdh and 10gbe transmission standards. the standard operating range is from 9.953 gbps to 11.1 gbps. figure 1, system block diagram , shows a typical network application. overview the S19235 can be used to implement the front end of sonet/sdh/fec/ 10gbe equipment which consists primarily of the serial transmit interface and the serial receive interface. the system timing circuitry consists of a high- speed phase detector, clock dividers, and clock distribution. the device utilizes on-chip clock synthesis pll components that allow the use of a slower external clock reference, 155.52 mhz or 622.08 mhz (or equivalent fec/10gbe rate), in support of existing system clocking schemes. the low-jitter, 16-bit, low voltage differential signaling (lvds) interfaces guarantee compliance with the bit-error rate requirements of the telecordia and itu-t standards. s 1 9 2 3 5 amcc suggested interface devices verrazano (s2509) quad sts-48 sonet/sdh/ digital wrapper backplane serdes ganges (s19202) sts-192 pos/atm sonet/ sdh mapper ganges ii (s19202) sts-192 pos/atm sonet/ sdh mapper hudson (s19203) variable rate digital wrapper framer/deframer, performance monitor, and fec device mekong (s19204) sts-192 pointer processor khatanga (s19205) sts-192c sonet/sdh framer/mapper with integrated mac s3390 10 gbps tia general features operational from 9.953 gbps to 11.1 gbps low power (1100 mw typical) 1.2 v and 1.8/2.5/3.3 v power supply built-in self test (bist) feature with error counter on-chip high-frequency pll for clock generation and clock recovery 16-bit lvds parallel data path tx and rx lock detect indication serial and reference loop timing modes line and diagnostic loopback mode for faulty node identification operational temperature range up to 85c supports management data bus for control i/o complies with oif sfi-4/ telecordia/itu-t specifications 255 pbga package transmitter features reference frequency of 155.52 or 622.08 mhz (or equivalent fec/ 10gbe rate) continued on next page... figure 1. system block diagram orx otx orx otx amcc S19235 16 16 amcc ganges hudson mekong khatanga tia ld ld amcc ganges hudson mekong khatanga amcc S19235 tia 16 16
6290 sequence drive san diego, ca 92121 tel: 858 450-9333 fax: 858 450-9885 http://www.amcc.com amcc reserves the right to make changes to its products, or to discontinue any product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied upon is current. amcc is a registered trademark of applied micro circuits corporation. copyright ? 2002 applied micro circuits corporation. all rights reserved. distribute only on a need-to-know basis, and subject to applicable nda. not to be disclosed to or used by any other person with out prior authorization. product brief S19235 oc-192 sonet/sdh/fec/gbe 16-bit transceiver pb1204_v2.01_10/03/03 2 empowering intelligen t optical networks confidential and proprietary the sequence of operations is as follows: transmitter operations 1. 16-bit parallel input 2. parallel-to-serial conversion 3. serial data output receiver operations 1. serial input to limiting post-amp 2. clock and data recovery 3. serial-to-parallel conversion 4. 16-bit parallel data and clock output internal clocking and control functions are transparent to the user. transmitter features (cont.) 155.52 mhz and 622.08 mhz (or equivalent fec/10gbe rate) clock outputs internal, self-initializing fifo to decouple transmit clocks programmable tsd output differential swing (for xfp and other applications) receiver features recovers clock from 9.953 to 11.1 gbps adaptive post-amplifier offset adjust for duty cycle distortion correction post-amplifier equalization adjust for 10 gbe jitter tolerance reference frequency of 155.52 mhz (or equivalent fec/ 10gbe rate) applications sonet/sdh-based transmission systems sonet/sdh modules 10gbe based transmission systems section repeaters add drop multiplexers (adm) broad-band cross-connects fiber optic terminators fiber optic test equipment figure 2. S19235 ordering information prefix package device s ? integrated circuit 19235 pb11 x xxxxx xx prefix device package
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